In high-speed electrical links, the transmitter's internal high-speed clock may leak (e.g., couple) to the transmit signal. The magnitude of the coupled clock may be as high as 5-10% of the transmit swing. The coupled clock signal may have a fundamental tone at the bit-rate frequency (since one edge may be used for every bit), and may have sub-harmonics at one half or one quarter of the bit-rate frequency. The coupled clock may reduce the signal to interference ratio at the receiver input and may increase bit-error ratio.
A serial link receiver may include DC offset cancellation circuits that may increase a receiver front end's sensitivity by canceling any DC offset caused by transistor mismatch or other sources. Offset cancellation may be done by shorting the P and N inputs of the differential input of the receiver and adjusting the offset so that the output of the analog front end (or “front-end”) is balanced around zero. In some cases, the bit-rate clock superimposed on the received signal may appear as a DC offset to the receiver samplers, because a sinusoid with frequency f0 sampled by a clock at rate f0 may appear as DC. As a result, it may be possible to cancel the effect of a coupled clock by utilizing the same circuits as those used for DC offset cancellation. To accomplish this, however, it may be necessary to cancel the total effective offset while the signal is transmitted from the transmitter to the receiver, and to de-couple the effect of the coupled clock from the transmit signal so that it may be measured and cancelled. This may be inconvenient, costly, or difficult to accomplish effectively.
Thus, there is a need for a system and method for the cancellation of coupled clock signals.